1. Field of the Invention
The method of system level static timing analysis disclosed herein is directed to the design and manufacturing of integrated circuit die. More specifically, but without limitation thereto, this method is directed to detecting timing violations in the design of an integrated circuit die.
2. Description of Related Art
System level static timing analysis is widely used in different aspects of physical design validation of an integrated circuit design. Traditionally, input and output (I/O) timing closure, for example, of a very large scale integrated circuit (VLSI) device is based on defining boundary constraints. This involves defining input delay, output delay, and the corresponding load on an output port. The input delay is set to constrain a setup/hold timing requirement on an input data port with respect to an input clock signal. The output delay defines an output delay constraint on an output data port with respect to an output clock signal. There are several ways to define clock signals in static timing analysis (STA), for example, a generated clock, a virtual clock, and so on. A generated clock is produced by a master clock by a clock divider or a gating circuit. The phase of a generated clock is maintained in a timing analysis perspective. A virtual clock has no real source in the integrated circuit design itself, that is, a virtual clock does not drive any clock pins. A virtual clock is used primarily as a reference clock edge for defining input/output requirements. These definitions of clock signals have been adequate for analyzing most I/O timing requirements.